Comparison of Various Optimized Architectures of DCO for ADPLL

Digitally controlled oscillator (DCO) form the core of all digital phase locked loop (ADPLL).Nowadays portable batteries play a vital role in communication systems, hence low power circuits with reduced hardware are important. These criterions are satisfied by the proposed architecture. Different DCO designs with 3T NAND and 3T NOR gates as inverters proposed along with the result of 3T XOR and 3T XNOR gates are compared.XOR based digitally controlled ring structure produces the frequency of [2.93 to 3.80 GHz] with power consumption of [293 to 369 μW] where as XNOR design produces [1.35 to 1.64 GHz] with power consumption of [195 to 223 μW]. The reported designs of NAND and NOR produces a frequency of [3.11 to 3.97 GHz] and [5.80 to 6.24 GHz] with power consumption of [293 to 369μW] and [841 to 858 μW] respectively. In this paper the proposed designs shows improvement in performance over the existing designs.